Bridging this gap is difficult the complexities of modern CMP memory hierarchy make it even harder: Data cache becomes shared among computing units, and the sharing is often non-uniform-whether two computing units share a cache depends on their proximity and the level of the cache. Consequently, data movement and storage is expected to consume more than 70% of the total system power. It is expected that by 2018, node concurrency in an exascale system will increase by hundreds of times, whereas, memory bandwidth will expand by only 10 to 20 times.

Despite the capped growth of the peak CPU speed, the aggregate speed of a CMP keeps increasing as more cores get into a single chip. The second hardware more » trend is the growing gap between memory bandwidth and the aggregate speed-that is, the sum of all cores' computing power-of a Chip Multiprocessor (CMP).

Some evidences are already shown on Graphic Processing Units (GPU): Irregular data accesses (e.g., indirect references A]) and conditional branches are limiting many GPU applications' performance at a level an order of magnitude lower than the peak of GPU. With more processors produced through a massive integration of simple cores, future systems will increasingly favor regular data-level parallel computations, but deviate from the needs of applications with complex patterns. The first is the increasing sensitivity of processors' throughput to irregularities in computation. The development of modern processors exhibits two trends that complicate the optimizations of modern software.

Network modeling and simulation tools